Aspects of the present invention are directed to a method to partially isolate nets to provide noise immunity.
On a typical chip or circuit design with millions of gates, nets and timing paths, an important design consideration is to prevent noise from certain nets from impeding signal propagation in other nets and thereby negatively affecting the timing of those nets. This consideration is, in fact, so important that in most cases the vast majority of late model timing paths of chips will be designed so carefully as to meet their timing requirements even if all the nets on the chip were being subjected to the maximum amount of coupled noise from adjacent nets.
Recently, a method of achieving correct timing in late model timing paths has been to conduct noise-induced timing violation sensitivity (NITVS) tests. The intent of NITVS tests is generally to identify and isolate only those nets that require wiring isolation to preclude coupled noise from negatively affecting the timing of the chip.
Unfortunately, there are drawbacks to such tests and to the isolation of a large number of nets. Among these is the fact that the chip being tested may have limited wiring resources available and that isolated nets use three times the wiring tracks that regular nets use and can increase wiring congestion. In addition, there may already be relatively high wiring congestion on some areas even without net isolation. In some cases, these areas can also be the most timing critical areas of the chip. Revisions of the chip design when wiring resources are limited and/or where congestion occurs can be complicated and time consuming.